RISC-V /Debug /Hart Info (hartinfo)

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Interpret as Hart Info (hartinfo)

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0dataaddr0datasize 0 (csr)dataaccess 0nscratch

dataaccess=csr

Description

This register gives information about the hart currently selected by {hartsel}.

This register is optional. If it is not present it should read all-zero.

If this register is included, the debugger can do more with the Program Buffer by writing programs which explicitly access the data and/or dscratch registers.

Fields

dataaddr

If {hartinfo-dataaccess} is 0: The number of the first CSR dedicated to shadowing the data registers.

If {hartinfo-dataaccess} is 1: Address of RAM where the data registers are shadowed. This address is sign extended giving a range of -2048 to 2047, easily addressed with a load or store using x0 as the address register.

datasize

If {hartinfo-dataaccess} is 0: Number of CSRs dedicated to shadowing the data registers.

If {hartinfo-dataaccess} is 1: Number of 32-bit words in the memory map dedicated to shadowing the data registers.

Since there are at most 12 data registers, the value in this register must be 12 or smaller.

dataaccess

0 (csr): The data registers are shadowed in the hart by CSRs. Each CSR is DXLEN bits in size, and corresponds to a single argument, per tab:datareg.

1 (memory): The data registers are shadowed in the hart’s memory map. Each register takes up 4 bytes in the memory map.

nscratch

Number of dscratch registers available for the debugger to use during program buffer execution, starting from {csr-dscratch0}. The debugger can make no assumptions about the contents of these registers between commands.

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